As an integrated circuit designer I can say that a lot of hardware is somewhat less complex than the software world. At the chip level anyway.
In the hardware world at the chip level, the environment is fairly rigid. A designer has a pretty good idea of what the environment is going to be for their chip. Linux is designed to operate in all sorts of environments: multiple cpu architectures, multiple versions of those architectures, the myriad peripherals, and all the other software that is going to run on linux.
That's not really the case with hardware at the chip level. We know what chip we are going to be talking to, or what family of chips. And most of those are designed in house, so there can be a lot of give-and-take going on.
It's just not a lot of combinations (compared to software, in my opinion.)
An exception would be memory, which is usually made by a third party. And it's also where you find incompatibilities... some manufacturer's ram doesn't work in macbook pros, etc. That's a bug.
And because the hardware can take a long time to iterate through design->implementation->verification->fabrication->prototype verification, there is a strong force driving designs toward being the simplest possible implementation that accomplishes the goals.
So you have these very well defined blocks of functionality that get pieced together and form a chip. The interfaces between blocks are very rigidly defined, and the amount of functionality in a given block is usually pretty limited.
At the level I work at, design is done in VHDL or Verilog (and now SystemVerilog is becoming a viable option). So that's a limited space. That could possibly be the biggest contributor to "less bugs" in hardware (if that is a true supposition). I get flustered with all the different software programming languages.
A big disadvantage of hardware design is that testing is first done in event based simulation. The tools available for this are pretty awesome, but it's still extremely slow. My last design would take about 100 hours to simulate about 300 ms of hardware time. That's a large part of why the iteration times are so long.
Now, with AMD and Intel, and designing these ridiculously highspeed CPUs, it's a whole different ball of wax. I expect a lot of their design is transistor level, full custom. Maybe they prototype in a higher level language, but you aren't going to 3GHz doing standard cell designs in VHDL.
Chip simulation seems like it would be a pretty difficult problem to multithread, since everything depends on everything else - can you run those simulation tools on clusters (or even GPGPU)?
Apparently Bulldozer, AMD's latest chip, is their first to start using automated design tools; one ex engineer claims that it resulted in 20% bigger and 20% slower designs:
In the hardware world at the chip level, the environment is fairly rigid. A designer has a pretty good idea of what the environment is going to be for their chip. Linux is designed to operate in all sorts of environments: multiple cpu architectures, multiple versions of those architectures, the myriad peripherals, and all the other software that is going to run on linux.
That's not really the case with hardware at the chip level. We know what chip we are going to be talking to, or what family of chips. And most of those are designed in house, so there can be a lot of give-and-take going on.
It's just not a lot of combinations (compared to software, in my opinion.)
An exception would be memory, which is usually made by a third party. And it's also where you find incompatibilities... some manufacturer's ram doesn't work in macbook pros, etc. That's a bug.
And because the hardware can take a long time to iterate through design->implementation->verification->fabrication->prototype verification, there is a strong force driving designs toward being the simplest possible implementation that accomplishes the goals.
So you have these very well defined blocks of functionality that get pieced together and form a chip. The interfaces between blocks are very rigidly defined, and the amount of functionality in a given block is usually pretty limited.
At the level I work at, design is done in VHDL or Verilog (and now SystemVerilog is becoming a viable option). So that's a limited space. That could possibly be the biggest contributor to "less bugs" in hardware (if that is a true supposition). I get flustered with all the different software programming languages.
A big disadvantage of hardware design is that testing is first done in event based simulation. The tools available for this are pretty awesome, but it's still extremely slow. My last design would take about 100 hours to simulate about 300 ms of hardware time. That's a large part of why the iteration times are so long.
Now, with AMD and Intel, and designing these ridiculously highspeed CPUs, it's a whole different ball of wax. I expect a lot of their design is transistor level, full custom. Maybe they prototype in a higher level language, but you aren't going to 3GHz doing standard cell designs in VHDL.